Low power digital circuit design

被引：0
|
作者：
Sakurai, T [1 ]
机构：
[1] Univ Tokyo, Ctr Collaborat Res, Meguro Ku, Tokyo 1538505, Japan
来源：
ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The paper describes approaches for achieving low power digital circuits. The approaches are classified from the standpoint of spatial granularity, temporal granularity and variable granularity. The trend is moving from coarse-grain to the finer grain to save more power with the higher engineering cost. The newer approach includes dynamic adaptive control of V-DD and V-TH at a block level. The paper also touches on low-power applications.
引用
收藏
页码：11 / 18
页数：8
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