Die Stacking using 3D-Wafer Level Packaging Copper/Polymer Through-Si Via Technology and Cu/Sn Interconnect Bumping

In this study, we report on the processing and the electrical characterization of a 3D-WLP TSV flow, Using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn microbump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 mu m. The actual TSV and microbump process uses 3 masks, two Si-DRIE steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 mu m empty set TSV, 5 mu m thick polymer liner, 25 mu m empty set Cu, 50 mu m deep TSV, and a 60 mu m TSV pitch.