Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture

被引:27
|
作者
Kim, Yoonjin [1 ]
Mahapatra, Rabi N. [1 ]
机构
[1] Texas A&M Univ, Dept Comp Sci, College Stn, TX 77843 USA
关键词
Coarse-grained reconfigurable architecture (CGRA); configuration cache; context architecture; embedded system; low power;
D O I
10.1109/TVLSI.2008.2006846
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Most of the coarse-grained reconfigurable architectures (CGRAs) are composed of reconfigurable ALU arrays and configuration cache (or context memory) to achieve high performance and flexibility. Specially, configuration cache is the main component in CGRA that provides distinct feature for dynamic reconfiguration in every cycle. However, frequent memory-read operations for dynamic reconfiguration cause much power consumption. Thus, reducing power in configuration cache has become critical for CGRA to be more competitive and reliable for its use in embedded systems. In this paper, we propose dynamically compressible context architecture for power saving in configuration cache. This power-efficient design of context architecture works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves up to 39.72% power in configuration cache with negligible area overhead (2.16%).
引用
收藏
页码:15 / 28
页数:14
相关论文
共 50 条
  • [1] Dynamic Context Management for Low Power Coarse-Grained Reconfigurable Architecture
    Kim, Yoonjin
    Mahapatra, Rabi N.
    [J]. GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, 2009, : 33 - 38
  • [2] Application Specific Optimization of Coarse-Grained Reconfigurable Architecture by Dynamic Context Compression
    Priyadharsini, S.
    Srilalitha, A.
    [J]. 2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
  • [3] Reusable context pipelining for low power coarse-grained reconfigurable architecture
    Kim, Yoonjin
    Mahapatra, Rabi N.
    [J]. 2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8, 2008, : 3379 - 3386
  • [4] Dynamically Compressible Context Architecture for Low Power Coarse-Grained Reconfigurable Array
    Kim, Yoonjin
    Mahapatra, Rabi N.
    [J]. 2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, 2007, : 395 - 400
  • [5] Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture
    Kim, Yoonjin
    Mahapatra, Rabi N.
    Park, Ilhyun
    Choi, Kiyoung
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (05) : 593 - 603
  • [6] Dynamic Context Management for Coarse-grained Reconfigurable Array DSP Architecture
    Liu, Yanliang
    Dai, Peng
    Wang, Xin'an
    Zhang, Xing
    Wei, Lai
    Zhou, Yan
    Sun, Yachun
    [J]. 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 79 - 82
  • [7] EReLA: A Low-Power Reliable Coarse-Grained Reconfigurable Architecture Processor and Its Irradiation Tests
    Yao, Jun
    Saito, Mitsutoshi
    Okada, Shogo
    Kobayashi, Kazutoshi
    Nakashima, Yasuhiko
    [J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2014, 61 (06) : 3250 - 3257
  • [8] Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture
    Yin, Shouyi
    Yin, Chongyong
    Liu, Leibo
    Zhu, Min
    Wei, Shaojun
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2012, E95D (02): : 335 - 344
  • [9] A Coarse-Grained Reconfigurable Approach for Low-Power Spike Sorting Architectures
    Carta, Nicola
    Sau, Carlo
    Pani, Danilo
    Palumbo, Francesca
    Raffo, Luigi
    [J]. 2013 6TH INTERNATIONAL IEEE/EMBS CONFERENCE ON NEURAL ENGINEERING (NER), 2013, : 439 - 442
  • [10] Coarse-grained reconfigurable architecture with low cost configuration data compression mechanism
    Tanigawa, K
    Kawasaki, T
    Hironaka, T
    [J]. 2003 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS, 2003, : 311 - 314