Pseudorandom number generator based on a 5D hyperchaotic four-wing memristive system and its FPGA implementation PRNG based on a 5D hyperchaotic four-wing memristive system and its FPGA implementation

被引:50
|
作者
Yu, Fei [1 ,2 ]
Li, Lixiang [1 ]
He, Binyong [1 ]
Liu, Li [1 ]
Qian, Shuai [1 ]
Zhang, Zinan [1 ]
Shen, Hui [1 ]
Cai, Shuo [1 ]
Li, Yi [3 ]
机构
[1] Changsha Univ Sci & Technol, Sch Comp & Commun Engn, Changsha 410114, Peoples R China
[2] Guilin Univ Elect Technol, Guangxi Key Lab Cryptog & Informat Secur, Guilin 541004, Peoples R China
[3] Hunan Post & Telecommun Planning & Designing Inst, 236 Yuanda Rd, Changsha 410126, Peoples R China
来源
EUROPEAN PHYSICAL JOURNAL-SPECIAL TOPICS | 2021年 / 230卷 / 7-8期
基金
中国国家自然科学基金;
关键词
NEURAL-NETWORKS; DYNAMIC-ANALYSIS; CIRCUIT-DESIGN; CHAOTIC SYSTEM; SYNCHRONIZATION; SECURITY; COMMUNICATION; ENTROPY; ROBUST; MAP;
D O I
10.1140/epjs/s11734-021-00132-x
中图分类号
O4 [物理学];
学科分类号
0702 ;
摘要
Pseudorandom numbers are widely used in information encryption, spread spectrum communication and other science and technology and engineering fields. Because chaos is very sensitive to the initial conditions and has good inherent pseudo-random characteristics, the research of pseudorandom number generator (PRNG) based on a chaotic system becomes a new beneficial exploration. This paper presents a FPGA PRNG based on a 5D hyperchaotic four-wing memristive system (HFWMS). The 5D HFWMS has multiline equilibrium and three positive Lyapunov exponents, which indicates that the system has very complex dynamic behavior. On this basis, a FPGA PRNG based on the 5D HFWMS is proposed. The proposed PRNG is implemented in VHDL language, modeled and simulated on Vivado 2018.3 platform, and synthesized by FPGA device ZYNQ-XC7Z020 on Xilinx. The post-processing module consists of 16 linear shift registers and 15 levels XOR chain. The maximum operating frequency is 138.331 MHz and the speed is 15.37 Mbit/s. The random bit sets generated by PRNG are further verified by NIST 800.22 statistical standard. The security is analyzed by dynamic degradation, keyspace, key sensitivity and correlation. Experiments show that the design can be applied to various embedded password applications.
引用
收藏
页码:1763 / 1772
页数:10
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