Gate Failure Physics of SiC MOSFETs Under Short-Circuit Stress

被引：71

作者：

Liu, Jingcun ^{[1
]}

Zhang, Guogang ^{[1
]}

Wang, Bixuan ^{[1
]}

Li, Wanping ^{[1
]}

Wang, Jianhua ^{[1
]}

机构：

[1] Xi An Jiao Tong Univ, State Key Lab Elect Insulat & Power Equipment, Xian 710049, Shaanxi, Peoples R China

来源：

IEEE ELECTRON DEVICE LETTERS | 2020年 / 41卷 / 01期

关键词：

Failure analysis; high temperature; multi-physics; power MOSFETs; reliability; silicon carbide; POWER MOSFETS; ROBUSTNESS; OXIDE; DEGRADATION;

D O I：

10.1109/LED.2019.2953235

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The unique gate failure mode of SiC MOSFETs is often identified but has not been fully understood yet. In this letter, post-failure cell inspections demonstrate that its main cause is the crack at the SiO2 dielectric layer with melted source aluminum inside. An electro-thermal-mechanical simulation is performed to reproduce the failure transition, and it reveals that the crack forms at an early stage. This new failure mechanism further enlightens on the vulnerability of the vertical power MOSFET structure in extremely high-temperature operation.

引用

页码：103 / 106

页数：4

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