4-Bit Ripple Carry Adder of Two-Phase Clocked Adiabatic Static CMOS Logic: A Comparison with Static CMOS

被引：3

作者：

Anuar, Nazrul ^{[1
]}

Takahashi, Yasuhiro ^{[2
]}

Sekine, Toshikazu ^{[2
]}

机构：

[1] Gifu Univ, Grad Sch Engn, 1-1 Yanagido, Gifu 5011193, Japan

[2] Gifu Univ, Fac Engn, Gifu 5011193, Japan

来源：

2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年

关键词：

D O I：

10.1109/ECCTD.2009.5274985

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.

引用

页码：65 / +

页数：2

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