A low-power 2.1 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic

被引：0
|
作者：
Ge, Y [1 ]
Jung, SO [1 ]
Kim, SH [1 ]
Kang, SM [1 ]
机构：
[1] Univ Calif Santa Cruz, Santa Cruz, CA 95064 USA
来源：
2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A high-speed, low-power 32-bit carry lookahead adder is presented. We have developed Dual Path All-N-Logic(DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. This adder can operate at frequencies up to 2.1GHz for 0.35um 1P4M CMOS technology and is 31.3% and 27.3% faster than the adders using All-N-Transistor(ANT) and All-N-Logic(ANL), respectively. It also consumes 29.2% and 15.4% less power than the ANT adder and ANL adder, respectively.
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页码：298 / 301
页数：4
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