High-frequency CMOS low-power single-branch continuous-time filters

A low-power CMOS continuous-time filter is presented. The filter implements a linearization technique which consists in compensating the driver non-linearity with an opposite load non-linearity. This results in requiring a tower overdrive to MOS devices and so in power saving. In additon to this the filter features other caractieristics which allows to reduce power consumption. They are: no parasitic poles, no CMFB, no body effect. Finally using digital tuning the performance are optimized for any operation condition. A prototype cell has been designed in a standard 0.5 mu m CMOS technology. With a pole frequency in the range 13MHz-83MHz (Q=1), the cell features a linear range (1%THD) of 400mVpp from a 3.3V supply. The parasitic capacitance are kept lower that 20% of the total capacitance. The power consumption in the tuning range varies from 6mW to 16mW.