Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits

被引：0

作者：

Shen, Shiue-Tsung ^{[1
]}

Liu, Wei-Hsiao ^{[1
]}

Ma, En-Hua ^{[1
]}

Li, James Chien-Mo ^{[1
]}

Cheng, I-Chun ^{[2
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Lab Dependable Syst, Taipei, Taiwan

[2] Natl Taiwan Univ, Grad Inst Photon & Optoelect, Dept Elect Engn, Taipei, Taiwan

来源：

2009 ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2009年

关键词：

THIN-FILM TRANSISTORS; INSTABILITY MECHANISMS; BIAS DEPENDENCE; STABILITY; GLASS; TIME;

D O I：

10.1109/ATS.2009.68

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents Very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin film transistor (a-Si TFT) technology. The proposed VLV, testing is an economic alternative to burn-ill because the former is non-destructive and can be easily performed on regular ATE in a short time. 140 circuits under test (CUT) of two different design styles are implemented in 8 mu m a-Si TFT technology on the glass substrate. All CUT are tested both at nominal voltage (10V) and very low voltage (7V), followed by a 200 second voltage stress at 30%. Seven unreliable CUT that escape nominal voltage (NV) testing are successfully caught by VLV testing and there is no CUT that is caught by NV testing but escapes VLV testing. The results indicate that VLV testing is more effective than NV testing in screening out unreliable a-Si TFT circuits.

引用

页码：75 / +

页数：2

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