SAT Encoding-based Verification of Sneak Path Problem in Via-switch FPGA

被引：0
|
作者：
Doi, Ryutaro [1 ,2 ]
Hashimoto, Masanori [1 ]
机构：
[1] Osaka Univ, Grad Sch Informat Sci & Technol, Dept Informat Syst Engn, Suita, Osaka, Japan
[2] Japan Soc Promot Sci, Tokyo, Japan
来源：
2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) | 2018年
关键词：
D O I：
10.1109/ISVLSI.2018.00084
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
FPGA that introduces via-switches, a kind of non-volatile resistive RAMs, for crossbar implementation is drawing attention due to higher integration density and performance. However, programming those switches arbitrarily in a crossbar is not trivial since a programming voltage must be given through signal wires that are shared by multiple via-switches. Consequently, depending on the previous programming status, unintentional switch programming may occur due to signal detour, which is called sneak path problem. This paper encodes programming operations in via-switch based crossbar into a satisfiability problem and rigidly verifies the sneak path problem. Verification results show that sneak path problems can be solved by imposing a specific programming constraint.
引用
收藏
页码：429 / 434
页数：6
相关论文
共 32 条
  • [1] Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA
    Doi, Ryutaro
    Yu, Jaehoon
    Hashimoto, Masanori
    2018 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) DIGEST OF TECHNICAL PAPERS, 2018,
  • [2] Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA
    Doi, Ryutaro
    Yu, Jaehoon
    Hashimoto, Masanori
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (10) : 2572 - 2587
  • [3] Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars
    Ochi, Hiroyuki
    Yamaguchi, Kosei
    Fujimoto, Tetsuaki
    Hotate, Junshi
    Kishimoto, Takashi
    Higashi, Toshiki
    Imagawa, Takashi
    Doi, Ryutaro
    Tada, Munehiro
    Sugibayashi, Tadahiko
    Takahashi, Wataru
    Wakabayashi, Kazutoshi
    Onodera, Hidetoshi
    Mitsuyama, Yukio
    Yu, Jaehoon
    Hashimoto, Masanori
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (12) : 2723 - 2736
  • [4] Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation
    Bai, Xu
    Banno, Naoki
    Miyamura, Makoto
    Nebashi, Ryusuke
    Okamoto, Koichiro
    Numata, Hideaki
    Iguchi, Noriyuki
    Hashimoto, Masanori
    Sugibayashi, Tadahiko
    Sakamoto, Toshitsugu
    Tada, Munehiro
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (07) : 2250 - 2262
  • [5] Range Encoding-Based Network Verification in SDN
    Tseng, Yen-Lun
    Chang, Guey-Yun
    Shih, Chun-Chung
    Liu, Yue-Xin
    Wu, Tien-Hsiang
    2016 IEEE 14TH INTL CONF ON DEPENDABLE, AUTONOMIC AND SECURE COMPUTING, 14TH INTL CONF ON PERVASIVE INTELLIGENCE AND COMPUTING, 2ND INTL CONF ON BIG DATA INTELLIGENCE AND COMPUTING AND CYBER SCIENCE AND TECHNOLOGY CONGRESS (DASC/PICOM/DATACOM/CYBERSC, 2016, : 400 - 405
  • [6] Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA
    Doi, Ryutaro
    Bai, Xu
    Sakamoto, Toshitsugu
    Hashimoto, Masanori
    PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020), 2020, : 983 - 986
  • [7] [Invited] AI, IoT Acceralation with "via-switch" FPGA and High Level Synthesis
    Wakabayashi, Kazutoshi
    PROCEEDINGS OF 2017 7TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS, DESIGN, AND VERIFICATION (ICDV), 2017, : 33 - 33
  • [8] A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA
    Doi, Ryutaro
    Bai, Xu
    Sakamoto, Toshitsugu
    Hashimoto, Masanori
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2020, E103A (12) : 1447 - 1455
  • [9] Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization
    Higuchi, Tatsuhiro
    Ishihara, Tohru
    Onodera, Hidetoshi
    2018 31ST IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2018, : 112 - 117
  • [10] Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications
    Hashimoto, Masanori
    Bai, Xu
    Banno, Naoki
    Tada, Munehiro
    Sakamoto, Toshitsugu
    Yu, Jaehoon
    Doi, Ryutaro
    Araki, Yusuke
    Onodera, Hidetoshi
    Imagawa, Takashi
    Ochi, Hirovuki
    Wakabayashi, Kazutoshi
    Mitsuyama, Yukio
    Suuibayashi, Tadahiko
    2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), 2020, : 502 - +
1234