Designs for reducing test time of distributed small embedded SRAMs

被引：0

作者：

Wang, BS ^{[1
]}

Wu, YJ ^{[1
]}

Ivanov, A ^{[1
]}

机构：

[1] Univ British Columbia, Dept Elect & Comp Engn, SOC Lab, Vancouver, BC V6T 1Z4, Canada

来源：

19TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2004年

关键词：

distributed small embedded SRAMs; data retention fault test; response analysis; test time;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in [4, 5]. The improvements are mainly two-fold. On one hand, the testing of time-consuming Data Retention Faults (DRFs), that is neglected by the test architecture in [4, 5], is now considered and performed via a DFT technique referred to as the "No Write Recovery Test Mode (NWRTM)". On the other hand, a parallel Local Response Analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained in [4, 5], with a negligible area cost.

引用

页码：120 / 128

页数：9

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