DEFECT ASSESSMENT IN AIN NUCLEATION LAYERS GROWN ON SILICON AND SILICON-ON-INSULATOR SUBSTRATES

被引：0

作者：

Simoen, E. ^{[1
,2
]}

Zhang, W. ^{[3
]}

Zhang, J. ^{[3
]}

Claeys, C. ^{[4
]}

Zhao, M. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Univ Ghent, Dept Solid State Sci, Krijgslaan 281 S1, B-9000 Ghent, Belgium

[3] Xidian Univ, Sch Microelect, South Taibai Rd 2, Xian 710071, Shaanxi, Peoples R China

[4] Katholieke Univ Leuven, Electr Eng Dept, Kasteelpk Arenberg 10, B-3001 Leuven, Belgium

来源：

2019 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC) | 2019年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Traps in AlN nucleation layers on bulk silicon and Silicon-on-Insulator (SOI) substrates have been studied by Capacitance-Voltage and low-frequency gate current noise measurements. Both methods indicate a lower trap density for the layers on SOI, suggesting a better quality AlN layer from a viewpoint of electrically active defects.

引用

页数：3

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