FPGA implementation of a median filter

The median filter is an effective device for the removal of impulse-based noise on video signals. This is due to the partial averaging effect of the median filter and its biasing of the input stream, rather than straight mathematical averaging. In this paper, we describe three realizations of median filter, built into as few as one Field programmable logic device, which is capable of processing an incoming video data stream at a maximum (programmable logic device partially dependent) of around 30 MS/s. In total, four designs are considered, with a primary design, two variations on the primary design and an asynchronous version based on the primary design. Simulation of the primary design (both synchronous and asynchronous) has demonstrated its potential for reducing the area requirements of a median filter whilst not sacrificing either speed or accuracy.