As the critical dimension (CD) is scaled into nanometer dimensions, operating frequencies exceed a gigahertz, and more functional blocks are added into systems on chip (SoC), interconnect has become a bottleneck in achieving the system performance [1]. In addition, scaling increases the impact of systematic intra-die CID variation (gate and metal linewidth variations) and this variation interacts with the circuit design by degrading circuit speed [2]. One major source of CD variation is the optical lithography process [3]. To determine how the lithography variation impacts circuit performance, this paper introduces a method to incorporate the lithography-caused interconnect linewidth variation in timing simulation. ISCAS benchmark circuits are used to evaluate the circuit performance impact of each optical effect.
