Design and Simulation of 10-Bit SAR ADC for Low Power Applications Using 180nm Technology

被引：0

作者：

Naveen, I. G. ^{[1
]}

Sonoli, Savita ^{[2
]}

机构：

[1] Sir MVIT Bangalore, Dept Elect & Commun Engn, Bangalore, Karnataka, India

[2] RYMEC, Dept Elect & Commun Engn, Ballari, Karnataka, India

来源：

2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER AND OPTIMIZATION TECHNIQUES (ICEECCOT) | 2016年

关键词：

Analog-to-Digital converter; SAR ADC; Capacitive DAC; Dynamic Latch Comparator;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Analog-to-Digital converters plays vital role in medical and signal processing applications. Normally low power ADC's were required for long term and battery operated applications. SAR ADC is best suited for low power, medium resolution and moderate speed applications. This paper presents a 10-bit low power SAR ADC which is simulated in 180nm CMOS technology. Based on literature survey, low power consumption is attained by using Capacitive DAC. Capacitive DAC also incorporate Sample-and-Hold circuit in it. Dynamic latch comparator is used to increase in speed of operation and to get lower power consumption.

引用

页码：331 / 335

页数：5

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