Simple design criterion for maximizing data rate in NoC links

A simple design criterion is presented for obtaining maximal data rate in network on chip (NoC) links. It is shown that the maximal data rate is achieved near the boundary between RC and RLC model validity domains. The criterion is applicable to various on-chip transmission line structures, including crossing lines at adjacent metal layers. Inductive effects are represented by time-of-flight through the link structure. The resulting design criterion can be expressed using only static RC wire parameters.