Electroencephalogram System Based on CMOS Analog Front-End Interleaved Chain Architecture

CMOS Analog Front-End (AFE) interleaved chain architecture for EEG detection system is presented. The proposed chain consists of three stages; the first and the third stages are amplifiers, while the second stage is dual-notch low pass filter (DNLPF). A basic building block is based on operational transconductance amplifier (OTA) with digitally programmable feature. It is used to realize amplifier and DNLPF stages. The first stage is the cascaded instrumentation amplifier (CIA) which offers a fixed gain of 31dB with high pass cutoff frequency at 1Hz. Due to powerline interference; DNLPF is designed to have two notches at 50Hz and at 150Hz. The second notch is used to reject third harmonic of powerline signal. The variable gain amplifier (VGA) provides controllable gain (25dB-47dB). PSpice post layout simulation results for the extracted AFE using 0.25 mu m CMOS process and operating under +/- 0.8V supply voltage are also given. AFE has a gain ranging from 47dB to 68dB, a power dissipation of 27 mu W, and input referred noise (IRN) of 4 mu V/root Hz.