ESD Robust Fully Salicided 5-V Integrated Power MOSFET in Submicron CMOS

被引：5

作者：

Lee, Jian-Hsing ^{[1
]}

Iyer, Natarajan Mahadeva ^{[2
]}

Prabhu, Manjunatha ^{[1
]}

机构：

[1] GLOBALFOUNDRIES Inc, ESD LU Dept, Malta, NY 12020, Malta

[2] GLOBAL FOUNDRIES Inc, Reliabil Engn Dept, Malta, NY 12020, Malta

来源：

IEEE ELECTRON DEVICE LETTERS | 2017年 / 38卷 / 05期

关键词：

Power-management integrated circuit (PMIC); electrostatic discharge (ESD); transmission-line pulse (TLP); LAYOUT; NMOS;

D O I：

10.1109/LED.2017.2686638

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel high electrostatic discharge (ESD), robust fully salicided 5-V integrated CMOS power MOSFET design is developed and demonstrated without the use of conventional salicide blocking ballast resistor. This scheme builds the ballast resistors on the top of the source and drain, without any increase in silicon footprint unlike prior methods, while maintaining standard transistor parametric performance.

引用

页码：623 / 625

页数：3

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