Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor

被引：7

作者：

Kim, D. ^{[1
]}

Kim, K. ^{[1
]}

Kim, J. -Y. ^{[1
]}

Lee, S. ^{[1
]}

Yoo, H. -J. ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Div Elect Engn, Sch EECS, Taejon 305701, South Korea

来源：

IET COMPUTERS AND DIGITAL TECHNIQUES | 2009年 / 3卷 / 05期

关键词：

ARCHITECTURE; MPEG-4;

D O I：

10.1049/iet-cdt.2008.0085

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

For flexible mapping of various task-level pipelines on a multi-core processor, the authors proposed the memory-centric network-on-chip (NoC). The memory-centric NoC manages producer-consumer data transactions between the tasks in the case of task-level pipelines are distributed over multiple processing cores. Since the memory-centric NoC manages the data transactions, it relieves burden of the software running on the processing cores and this results in power-efficient execution of task-level pipeline. To prove advantages of the memory-centric NoC, the authors implemented a multi-core processor based on the memory-centric NoC.

引用

页码：513 / 524

页数：12

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