An FPGA-based cortical and thalamic silicon neuronal network

被引：0

作者：

Nanami, Takuya ^{[1
]}

Kohno, Takashi ^{[2
]}

机构：

[1] Univ Tokyo, Sch Engn, Tokyo, Japan

[2] Univ Tokyo, Inst Ind Sci, Tokyo, Japan

来源：

PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON ARTIFICIAL LIFE AND ROBOTICS (ICAROB 2016) | 2016年

关键词：

silicon neuronal network; neuron model; FPGA; cortex; thalamus; MODEL;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A DSSN model is a neuron model which is designed to be implemented efficiently by digital arithmetic circuit. In our previous study, we expanded this model to support the neuronal activities of several cortical and thalamic neurons; Regular spiking, fast spiking, intrinsically bursting and low-threshold spike. In this paper, we report our implementation of this expanded DSSN model and a kinetic-model-based silicon synapse on an FPGA device. Here, synaptic efficacy was stored in block RAMs, and external connection was realized based on a bus that conform to the address event representation. We simulated our circuit by the Xilinx Vivado design suit.

引用

页码：134 / 137

页数：4

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