Embedded system level self-test for mixed-signal IO verification

This article presents an embedded system level self-test implementation for verification of a peripheral and its connectivity to the system. The self-test enables to perform a test for verifying the 10 connectivity from inside the system. The proposed on-chip-testing scheme exploits IC level CMOS testability structures. The IC level DFT structure is verified. The scheme is confirmed by minor silicon overhead. The system level methodology is applied for a peripheral test. The methodology is evaluated by analyzing the response signal and by making a histogram data analysis. The applicability of the methodology is evaluated by comparing it to the existing methods. The article will define the approach, will list the main benefits of this methodology, analyze the laboratory test results,and show the changes that need to be implemented in a mixed-signal IC in order to achieve this system level testability.