An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits

Due to time-consuming SPICE simulations and extremely low failure rules, yield optimization for large static random access memory (SRAM) circuits is still a challenging problem. In this paper, a novel robust yield optimization problem is firstly proposed for SRAM circuits, where robust means considering design and process parameter variations simultaneously. Both a multi-fidelity Gaussian process regression model, which utilizes the strong nonlinear relationship between small and large SRAM columns, and a Bayesian optimization framework are applied to guide the sampling of the expensive large SRAM circuits. A multi-modal problem is formulated to find all peaks and valleys on the small SRAM circuits. Such precompulalional knowledge can accelerate the convergence of the proposed multi-fidelity and Bayesian optimization framework. Experimental results show that robust yield is essential to yield optimization, for traditional optimal design will degenerate with 4-5 orders of magnitude of yields, if design variations considered, and it doesn't coincide with the new optimum under the robust yield. The proposed method can gain a 3 similar to 4x speedup compared to the state-of-the-art method without loss of accuracy.