Highly Robust Nanoscale Planar Double-Gate MOSFET Device and SRAM Cell Immune to Gate-Misalignment and Process Variations

被引：0

作者：

Sachid, Angada B. ^{[1
]}

Kulkarni, Giri S. ^{[1
]}

Baghini, Maryam S. ^{[1
]}

Sharma, Dinesh K. ^{[1
]}

Rao, V. Ramgopal ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Ctr Excellence Nanoelect, Bombay 400076, Maharashtra, India

来源：

2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY | 2009年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Gate misalignment and process variations are important challenges in sub-20 nm gate length planar double-gate (DG) MOSFET devices For the first time, we demonstrate a misalignment- and process variations-aware device optimization strategy for a DG-MOSFET Using underlaps and high-kappa offset-spacers, we show that the robustness of the device to gate misalignment and process variations can be improved. A standard 6T-SRAM cell designed using the optimized devices shows better read and hold static noise margins, and lower variations in SNM and leakage power compared to a conventional DG-MOSFET.

引用

页码：13 / 16

页数：4

共 50 条

[1] Vertical Double-Gate MOSFET Device Technology
Masahara, Meishoku
Liu, Yongxun
Endo, Kazuhiko
Matsukawa, Takashi
Suzuki, Eiichi
[J]. ELECTRONICS AND COMMUNICATIONS IN JAPAN, 2008, 91 (01) : 46 - 51
[2] A compact scattering model for the nanoscale double-gate MOSFET
Rahman, A
Lundstrom, MS
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (03) : 481 - 489
[3] Shielded channel double-gate MOSFET: A novel device for reliable nanoscale CMOS applications
Orouji, AA
Kumar, MJ
[J]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (03) : 509 - 514
[4] Dual-Material Double-Gate SOI n-MOSFET: Gate Misalignment Analysis
Sharma, Rupendra Kumar
Gupta, Ritesh
Gupta, Mridula
Gupta, R. S.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (06) : 1284 - 1291
[5] Compact Quantum Modeling Framework for Nanoscale Double-Gate MOSFET
Monga, Udit
Fjeldly, T. A.
[J]. NANOTECH CONFERENCE & EXPO 2009, VOL 3, TECHNICAL PROCEEDINGS: NANOTECHNOLOGY 2009: BIOFUELS, RENEWABLE ENERGY, COATINGS FLUIDICS AND COMPACT MODELING, 2009, : 580 - 583
[6] Modeling and simulation of the diffusive transport in a nanoscale Double-Gate MOSFET
P. Pietra
N. Vauchelet
[J]. Journal of Computational Electronics, 2008, 7 : 52 - 65
[7] Modeling and simulation of the diffusive transport in a nanoscale Double-Gate MOSFET
Pietra, P.
Vauchelet, N.
[J]. JOURNAL OF COMPUTATIONAL ELECTRONICS, 2008, 7 (02) : 52 - 65
[8] Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs
Yin, CS
Chan, PCH
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (01) : 85 - 90
[9] Independent-gate controlled asymmetrical SRAM cells in double-gate MOSFET technology for improved READ stability
Kim, Jae-Joon
Kim, Keunwoo
Chuang, Ching-Te
[J]. ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2006, : 74 - +
[10] Independent-gate controlled asymmetrical SRAM cells in double-gate MOSFET technology for improved READ stability
Kim, Jae-Joon
Kim, Keunwoo
Chuang, Ching-Te
[J]. ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2006, : 73 - +

← 1 2 3 4 5 →