A 9.3-GHz-Tuning-Range, 58-GHz CMOS Direct Injection-Locked Frequency Divider Using Input-Power-Matching Technique

被引：0

作者：

Hsu, Wei-Lun ^{[1
]}

Chen, Chang-Zhi ^{[1
]}

Lin, Yo-Sheng ^{[1
]}

Chang, Jin-Fa ^{[1
]}

机构：

[1] Natl Chi Nan Univ, Dept Elect Engn, Puli, Taiwan

来源：

2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4 | 2009年

关键词：

CMOS; power-matching technique; direct injection-locked frequency-divider (DILFD); wide locking range;

D O I：

10.1109/ECTC.2009.5074270

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 58-GHz (V-band) CMOS direct injection-locked frequency-divider (DILFD) using input-power-matching technique for locking-range enhancement is reported for the first time. In an input-power-matching technique, an inductive input-matching-network is added to the gate of the NMOS switch to optimize the input-power-matching, i.e. to maximize the internal power, over the frequency band of interest. This DILFD architecture also features a very low input capacitance; therefore, high operating frequency of 58.2 GHz can be achieved. The DILFD dissipated 8.45 mW power from a 1.3 V power supply, and achieved a total locking range of 9.3 GHz (48.9-58.2 GHz; 17.4%), which is 400% higher than that (1.86 GHz (3%)) of a traditional DILFD without the input-matching-network for comparison. The chip area was only 0.585x0.492 mm(2) excluding the test pads.

引用

页码：1846 / 1849

页数：4

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