An 865-μW H.264/AVC video decoder for mobile applications

被引：0

作者：

Liu, Tsu-Ming ^{[1
]}

Lin, Ting-An ^{[1
]}

Wang, Sheng-Zen ^{[1
]}

Lee, Wen-Ping ^{[1
]}

Hou, Kang-Cheng ^{[1
]}

Yang, Jiun-Yan ^{[1
]}

Lee, Chen-Yi ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, NCTU, Hsinchu, Taiwan

来源：

2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865pW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4x4 sub-block level pipelining that achieves better buffer allocation and decoding throughput. In addition, several modules are designed with new features to improve overall system throughput (up to 260,000 MacroBlock/sec). The proposed solution integrates 456-k logic gates with 161Kb of embedded SRAM in 0.18-mu m single-poly six-metal CMOS process with area of 11.3mm(2).

引用

页码：301 / 304

页数：4

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