Ultra-low voltage analog design techniques for nanoscale CMOS technologies

被引：14
|
作者：
Kinget, Peter [1 ]
Chatterjee, Shouri [1 ]
Tsividis, Yannis [1 ]
机构：
[1] Columbia Univ, Dept Elect Engn, New York, NY 10027 USA
来源：
2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS | 2005年
关键词：
D O I：
10.1109/EDSSC.2005.1635192
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper reviews the challenges and opportunities for ultra-low voltage analog integrated circuit design. The continuing scaling of CMOS technology feature sizes forces a proportional reduction of the supply voltage. The ultra-low supply voltages, down to 0.5 V, projected for the nanoscale CMOS technologies requires drastic changes in the basic circuit topologies used in analog integrated circuits. We explore the combined use of the gate and body terminal of the MOS transistor for signal input or bias control. We illustrate several true-low voltage OTA design and biasing techniques in a fully integrated 0.5 V varactor-C active filter implemented in a standard 0.18 mu m CMOS technology.
引用
收藏
页码：9 / 14
页数：6
相关论文
共 50 条
  • [1] Ultra-low voltage analog integrated circuits for nanoscale CMOS
    Kinget, Peter R.
    [J]. PROCEEDINGS OF THE 2007 IEEE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING (BCTM), 2007, : 144 - 148
  • [2] Ultra-Low Voltage Integrated Receivers in Nanoscale CMOS
    Balankutty, Ajay
    Kinget, Peter R.
    [J]. 2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
  • [3] Design Techniques for Ultra-Low Voltage Comparator Circuits
    Wang, Yao
    Wang, Haibo
    Wen, Guangjun
    [J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2015, 24 (01)
  • [4] Analog Circuit Design in Nanoscale CMOS Technologies
    Lewyn, Lanny L.
    Ytterdal, Trond
    Wulff, Carsten
    Martin, Kenneth
    [J]. PROCEEDINGS OF THE IEEE, 2009, 97 (10) : 1687 - 1714
  • [5] Energy Efficient and Ultra Low Voltage Security Circuits for Nanoscale CMOS Technologies
    Mathew, Sanu
    Satpathy, Sudhir
    Suresh, Vikram
    Krishnamurthy, Ram K.
    [J]. 2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2017,
  • [6] Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples
    Stopjakova, Viera
    Rakus, Matej
    Kovac, Martin
    Arbet, Daniel
    Nagy, Lukas
    Sovcik, Michal
    Potocny, Miroslav
    [J]. RADIOENGINEERING, 2018, 27 (01) : 171 - 185
  • [7] Ultra-low voltage analog integrated circuits
    Chatterjee, Shouri
    Tsividis, Yannis
    Kinget, Peter
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (06): : 673 - 680
  • [8] Ultra-Low Voltage CMOS Logic Circuits
    Melek, Luiz A. P.
    Schneider, Marcio C.
    Galup-Montoro, Carlos
    [J]. PROCEEDINGS OF THE 2014 ARGENTINE SCHOOL OF MICRO-NANOELECTRONICS, TECHNOLOGY AND APPLICATIONS (EAMTA), 2014, : 1 - 7
  • [9] Analog Circuit Design in Nanoscale CMOS Technologies Introduction
    O'Donnell, Richard
    [J]. PROCEEDINGS OF THE IEEE, 2009, 97 (10) : 1684 - 1686
  • [10] Design of Ultra-Low Voltage and Low-Power CMOS Current Bleeding Mixer
    Tan, G. H.
    Sidek, R. M.
    Isa, M. M.
    [J]. 2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2014, : 344 - 347
12345