Spike Trains Encoding Optimization for Spiking Neural Networks Implementation in FPGA

Deep Neural Networks (DNNs) such as convolutional neural networks (CNNs) have become state-of-the-art methods for diverse fields, such as computer vision, natural language processing and object tracking. However, DNNs face great challenges to implementation of real-time embedded system or edge devices because of the huge power dependence. Spiking neural network (SNN) is a type of biological plausibility model that performs information processing based on spikes, not continuous values, and is more hardware-friendly than DNNs. To enable SNNs to process information about natural images, we present a method to accelerate the spikes encoding on the Field Programmable Gate Array (FPGA). In addition, we demonstrate a low-power implementation of real-time system for digital recognition using multi-kernels parallel (16PEs) that just consumes 4.956W with 100Mhz frequency clock on Xilinx XCZU9EG Chip. This accelerator system has achieved about 4.1x than ARM CPU on the inference time consumption, and 17.7x than Intel-4790k CPU on the energy efficiency.