HARDWARE ARCHITECTURE FOR H.264/AVC INTRA 16X16 FRAME PROCESSING

被引：0

作者：

Loukil, H. ^{[1
]}

Arous, S. ^{[1
]}

Werda, I. ^{[1
]}

Ben Atitallah, A. ^{[2
]}

Kadionik, P. ^{[3
]}

Masmoudi, N. ^{[1
]}

机构：

[1] Univ Sfax, Natl Sch Engn, BP W, Sfax 3038, Tunisia

[2] Univ Sfax, High Inst Elect & Commun, Sfax 3018, Tunisia

[3] Univ Bordeaux 1, ENSEIRB, IMS Lab, CNRS UMR 5218, F-33405 Talence, France

来源：

2009 6TH INTERNATIONAL MULTI-CONFERENCE ON SYSTEMS, SIGNALS AND DEVICES, VOLS 1 AND 2 | 2009年

关键词：

intra prediction; quantization; integer transform; Hardware Implementation; VHDL; H.264; ALGORITHM;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present an efficient H.264/AVC Intra 16x16 Frame Coder System. The System achieves real-time performance for video conference applications. The INTRA 16X16 is composed by intra 16x16 prediction, integer transform, quantization AC, inverse integer transform, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The proposed hardware is implemented in VHDL. The VHDL RTL code works at 160 MHz in an Altera Stratix II FPGA and it code 129 Mpixels per second. This work will be used as an Intellectual Property (IP) integrated in H.264/AVC encoder.

引用

页码：633 / +

页数：3

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