Hardware Architecture for H.264/AVC INTRA 16X16 Frame Processing

被引：0

作者：

Loukil, H. ^{[1
]}

Arous, S. ^{[1
]}

Atitallah, A. Ben ^{[2
]}

Kadionik, P. ^{[3
]}

Masmoudi, N. ^{[1
]}

机构：

[1] Univ Sfax, Natl Sch Engn, BP W, Sfax 3038, Tunisia

[2] Univ Sfax, Inst High Elect & Commun, Sfax 3018, Tunisia

[3] Univ Bordeaux 1, CNRS, UMR 5218, IMS Lab ENSEIRB, F-33405 Talence, France

来源：

DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS | 2009年

关键词：

intra prediction; quantization; integer transform; Hardware Implementation; VHDL; H.264; ALGORITHM;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present an efficient H.264 / AVC Intra 16x16 Frame Coder System. The System achieves real-time performance for video conference applications. The INTRA 16X16 is composed by intra 16x16 prediction, integer transform, quantization AC, inverse integer transform, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The proposed hardware is implemented in VHDL. The VHDL RTL code works at 160 MHz in an Altera Stratix II FPGA and it code 129 Mpixels per second. This work will be used as an Intellectual Property (IP) integrated in H.264/AVC encoder.

引用

下载

页码：82 / +

页数：2

共 50 条

[1] HARDWARE ARCHITECTURE FOR H.264/AVC INTRA 16X16 FRAME PROCESSING
Loukil, H.
Arous, S.
Werda, I.
Ben Atitallah, A.
Kadionik, P.
Masmoudi, N.
2009 6TH INTERNATIONAL MULTI-CONFERENCE ON SYSTEMS, SIGNALS AND DEVICES, VOLS 1 AND 2, 2009, : 633 - +
[2] Hardware Design of T/Q/IQ/IT for Intra 16x16 in H.264/AVC
Gu, Meihua
Hao, Jinyan
EMERGING RESEARCH IN ARTIFICIAL INTELLIGENCE AND COMPUTATIONAL INTELLIGENCE, 2011, 237 : 310 - 317
[3] Requantization transcoding in pixel and frequency domain for intra 16x16 in H.264/AVC
De Cock, Jan
Notebaert, Stijn
Lambert, Peter
De Schrijver, Davy
Van de Walle, Rik
ADVANCED CONCEPTS FOR INTELLIGENT VISION SYSTEMS, PROCEEDINGS, 2006, 4179 : 533 - 544
[4] Hardware architecture design for H.264/AVC intra frame coder
Huang, YW
Hsieh, BY
Chen, TC
Chen, LG
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 269 - 272
[5] An efficient pipelined architecture for H.264/AVC intra frame processing
Jin, Genhua
Jung, Jin-Su
Lee, Hyuk-Jae
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 1605 - +
[6] Implicit Line-Based Intra 16x16 Prediction for H.264/AVC High-Quality Video Coding
Choi, Jung-Ah
Ho, Yo-Sung
CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2012, 31 (05) : 1829 - 1845
[7] A hardware architecture for intra-prediction of H.264/AVC
Lee, SJ
Kim, CG
Kim, MS
Kim, SD
ESA '05: PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS AND APPLICATIONS, 2005, : 222 - 228
[8] 16x16 Macroblock partition size prediction for H.264 P slices
You, Jongmin
Kim, Wonkyun
Jeong, Jechang
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2006, 52 (04) : 1377 - 1383
[9] General Architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC Intra Frame Transcoding
Lin, Yinyi
Hsu, He Han
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2011, 65 (01): : 89 - 103
[10] General Architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC Intra Frame Transcoding
Yinyi Lin
He Han Hsu
Journal of Signal Processing Systems , 2011, 65 : 89 - 103

← 1 2 3 4 5 →