A real-time edge detector: Algorithm and VLSI architecture

In this paper we present a very large scale integration (VLSI) architecture of a new edge detection algorithm, which has a very regular computational structure. The new algorithm detects weak edges and produces single-pixel localized edges. Due to its highly pipelined structure, the VLSI implementation of the algorithm outputs one edge-pixel every clock cycle, The VLSI architecture is a complete realization of the algorithm, where no degradation is introduced to the ASIC output when compared to edges produced by the algorithm. The detector is capable of processing video graphic array (VGA) sized images at 30 frames/s at a clock rate of 10 MHz in a stand-alone mode, where no additional glue logic is required. The ASIC was laid out and fabricated using Samsung's 0.8 mu m double-metal CMOS process. (C) 1997 Academic Press Limited.