Comparison of Four-Terminal DG MOSFET Compact Model with Thin Si Channel FinFET Devices

We discuss a compact model for four-terminal double-gate (DG) MOSFETs based on double charge-sheet drift-diffusion transport, with carrier-velocity saturation. In this model, large VD at the saturation region is attributed to the infiltrated drain electric field. The latter overrides the drift-diffusion model at the transition point where the quasi-Fermi level is smoothly connected. The model can handle asymmetric gate structure, as well as independent gate voltage for two gates. This approach provides physics-based carrier profile. Comparison with the result of 2D device simulator shows that accurate intrinsic capacitance model has been obtained by the analytical derivative of channel carrier with respect to the terminal voltages. The model was compared with the FinFET samples fabricated by using lightly doped p-type (110) SOI wafers. By fitting five geometrical factors, two flat-band voltages, four transport-related parameters, two extrinsic resistances, the model gives a quite acceptable device model.