A transformerless high gain dc-dc boost converter with reduced voltage stress

被引:44
|
作者
Zaid, Mohammad [1 ]
Khan, Shahrukh [1 ]
Siddique, Marif Daula [2 ]
Sarwar, Adil [1 ]
Ahmad, Javed [1 ]
Sarwer, Zeeshan [1 ]
Iqbal, Atif [2 ]
机构
[1] ZHCET Aligarh Muslim Univ, Dept Elect Engn, Aligarh, Uttar Pradesh, India
[2] Qatar Univ, Dept Elect Engn, Doha, Qatar
关键词
efficiency; high gain; voltage multiplier cell (VMC); voltage stress; TOPOLOGIES;
D O I
10.1002/2050-7038.12877
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a modified and improved high gain dc-dc boost converter is proposed. The converter has utilized two voltage multiplier cells (VMCs) comprising switched capacitors (SC) and switched inductors (SL) to increase the voltage gain of the converter. The basic concept of these switched topologies is that when the switch is ON, the energy is stored by the inductor and the capacitor transfers its energy to load and inductor. In the OFF cycle, the inductor transfers its energy to the capacitor, and, simultaneously, capacitor is charged through input voltage also. As compared to other nonisolated topologies, the proposed converter has a high voltage gain and low voltage stress across semiconductor devices. The voltage stress on all capacitors except the output capacitor is less than the voltage across the load. A detailed analysis of the converter in continuous conduction (CCM) and discontinuous conduction modes (DCM) is shown. The proposed converter has a peak efficiency of 94.8%. For the efficiency calculation of the proposed topology, PLECS software is used. The experimental results agree with the theoretical analysis and validate the working and performance of the proposed converter.
引用
收藏
页数:17
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