A unity-gain buffer with reduced offset and gain error

被引：2

作者：

Xing, Guangmao ^{[1
]}

Lewis, Stephen H. ^{[2
]}

Viswanathan, T. R. ^{[3
]}

机构：

[1] Univ Calif Davis, Marvell Semicond, Santa Clara, CA USA

[2] Univ Calif Davis, Davis, CA 95616 USA

[3] Univ Texas Dallas, Richardson, TX 75083 USA

来源：

PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

10.1109/CICC.2006.320831

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A unity-gain buffer has been fabricated in 0.35-mu m CMOS technology. The circuit uses feed forward and local feedback in a cascaded source follower circuit as well as two global feedback loops: one to reduce the output resistance, gain error, and offset and a second loop to further reduce gain error. The buffer consumes 3.7 mW at 3.3 V and has a bandwidth of 92 MHz when driving a 13-pF capacitive load.

引用

页码：825 / 828

页数：4

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