Speeding up simulation time in EEPROM memory designs

This paper presents an efficient technique to decrease siniulation time of EEPROM memory arrays. This technique is based on the complexity reduction Of an existing compact EEPROM model. This original model is Unsuitable when dealing with large memory arrays simulations. To overcome this limitation. we propose two alternative models which allow reducing time and ineniory space overheads when compared to the conipact model. The first EEPROM model (level 1) is as simple as possible and provides fast simulation time. The second model (level 2) is a compromise between the compact inodel and the level 1 model. We also present simulation fine results using these different models within memory arrays.