Design and Simulation of a Tunable 14-Bit IIR Digital Low-Pass Filter Based on FPGA

被引：1

作者：

Roshanpanah, Abolfazl ^{[1
]}

Borhanifar, Hossein ^{[1
]}

机构：

[1] Islamic Azad Univ, Sci & Res Branch, Dept Mech Elect Power & Comp, Tehran, Iran

来源：

2022 INTERNATIONAL CONFERENCE ON ADVANCED ENTERPRISE INFORMATION SYSTEM, AEIS | 2022年

关键词：

IIR low-pass filter; FPGA; VHDL; approximated coefficients;

D O I：

10.1109/AEIS59450.2022.00028

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A 5th-order tunable IIR digital low-pass filter is presented which can operate from 20 to 70 MHz at a 176-MHz sampling frequency. The number of input and output bits is 14 and 15, respectively. The main characteristics, e.g., frequency response, group delay, stability, the location of poles and zeros, and noise are investigated. The results of the systematic simulation confirm the accuracy of the filter's performance. Approximated filter coefficients are used to reduce the complexity of the circuit and increase the sampling frequency. A maximum frequency of 175.596 MHZ on FPGA is obtained using this technique.

引用

页码：152 / 156

页数：5

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