Design and Realization of Low-Pass Filter with the Adjustment of Stop Frequency Based on FPGA

被引：0

作者：

Shi Wei ^{[1
]}

Song Yue ^{[2
]}

Xiang Yuanhui ^{[3
]}

机构：

[1] Hunan Univ Technol, Coll Elect & Informat Engineer, Zhuzhou, Peoples R China

[2] Dongguan Univ Technol, Coll Elect Engn, Dongguan, Peoples R China

[3] Hunan Univ Sci & Technol, Coll Phys, Zhuzhou, Peoples R China

来源：

TECHNOLOGY AND APPLICATION OF ELECTRONIC INFORMATION | 2009年

关键词：

low-pass filter; stop frequency; pace; FPGA;

D O I：

暂无

中图分类号：

G40 [教育学];

学科分类号：

040101 ; 120403 ;

摘要：

According to the principium of signal sampling, A Low-pass Filter was designed based on FPGA. The attenuation of stop frequency is 30dB, the range of pass frequency is from 1KHz to 20KHz with 1KHz pace; the gain range of amplitude is from 0 to 40dB with 10dB pace, the result of experiment showed the design was feasible.

引用

页码：124 / +

页数：2