A unified polar decoder platform for low-power and low-cost devices

In this paper, we design a polar decoding platform for diverse application scenarios that require low-cost and lowpower communications. Specifically, prevalent polar decoders such as successive cancellation (SC), SC-list (SCL) and Fano decoders are all supported under the same architecture. Unlike high-throughput or low-latency decoders that promote parallelism, this architecture promotes serialization by repeatedly calling a "sub-process" that is executed by a core module. Surprisingly, the resulting serial SCL-8 decoder is only 3 times the size of an SC decoder, much smaller than the predicted 8 times. Cost and power are minimized through resource sharing and adaptive decoding techniques, etc. We carried out performance simulation and hardware implementation to evaluate the actual chip area and energy consumption.