Design of On-Chip Debug System for embedded processor

被引：0

作者：

Park, Hyungbae ^{[1
]}

Xu, Jingzhe ^{[1
]}

Park, Jusung ^{[1
]}

Ji, Jung-Hoon ^{[2
]}

Woo, Gyun ^{[2
]}

机构：

[1] Pusan Natl Univ, Dept Elect Engn, Pusan 609735, South Korea

[2] Pusan Natl Univ, Dept Comp Engn, Pusan 609735, South Korea

来源：

ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3 | 2008年

关键词：

GDB; JTAG; On-Chip Debugger;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we introduce On-Chip Debug System (OCDS) which supports symbolic debugging at c-level using OCD integrated Debug-logic into target processor. The OCDS consist of SW debugger that supports a functionality of symbolic debugging, OCD (On-Chip Debugger) serving as a debugger of internal state of target processor, and Interface & Control block interfacing SW debugger and OCD. After OCD block is interfaced with 32bit RISC processor core and then implemented with FPGA, OCD is connected by Interface & Control block, and SW debugger. The verification of the design is carried out through device recognition, carrying-out instructions of JTAG(Joint Test Action Group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting break-points and watch points.

引用

页码：652 / +

页数：2

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