A modified gm/ID design methodology for deeply scaled CMOS technologies

被引：17
|
作者：
Pollissard-Quatremere, Guillaume [1 ]
Gosset, Geoffroy [1 ]
Flandre, Denis [1 ]
机构：
[1] Catholic Univ Louvain, Dept Elect Engn ICTEAM ELEN, B-1348 Louvain, Belgium
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2014年 / 78卷 / 03期
关键词：
CMOS; Analog design; Design reuse; CAD methodology; Transistor sizing; Ultra-deep-submicron; g(m)/I-D; INTEGRATED-CIRCUITS; ANALOG CIRCUITS; PERFORMANCE; IMPACT;
D O I：
10.1007/s10470-013-0166-z
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an updated version of the g (m) /I (D) -based sizing methodology for advanced short-channel CMOS technologies. The objective of this technique is to quickly and accurately size any linear analog circuit, top-down, from some required specifications and evaluate the remaining ones. A database describing the underlying MOS technology is taken as input of the sizing script, making the sizing process technology and corner independent. An advanced CMOS technology is analyzed, underlining the limitations of the original g (m) /I (D) methodology and its past improvements, then the proposed methodology is described in detail and tested successfully on a double stage amplifier, using two different CMOS technologies in all process-voltage-temperature corners.
引用
收藏
页码：771 / 784
页数：14
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