A design methodology for hardware acceleration of adaptive filter algorithms in image processing

被引：18

作者：

Dutta, Hritam ^{[1
]}

Hannig, Frank ^{[1
]}

Teich, Juergen ^{[1
]}

Heigl, Benno ^{[2
]}

Hornegger, Heinz ^{[2
]}

机构：

[1] Univ Erlangen Nurnberg, Dept Comp Sci 12, D-8520 Erlangen, Germany

[2] Siemens AG, Med Solut, Forchheim, Germany

来源：

IEEE 17TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/ASAP.2006.4

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. The final architecture deliver similar synthesis results as a hand-tuned design.

引用

页码：331 / +

页数：2

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