Multi-Cell Soft Errors at the 16-nm FinFET Technology Node

被引：0

作者：

Tam, N. ^{[1
]}

Bhuva, B. L. ^{[2
]}

Massengill, L. W. ^{[2
]}

Ball, D. ^{[2
]}

McCurdy, M. ^{[2
]}

Alles, M. L. ^{[2
]}

Chatterjee, I. ^{[3
]}

机构：

[1] Marvell Semicond, San Jose, CA USA

[2] Vanderbilt Univ, Nashville, TN 37212 USA

[3] Univ Bristol, Bristol, Avon, England

来源：

2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2015年

关键词：

SRAM; FinFET technology; scaling; soft errors; TCAD modeling; multi-bit upsets; SINGLE-EVENT UPSETS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Soft error performance of 16-nm FinFET SRAM designs fabricated using a commercial bulk CMOS process is evaluated using heavy-ions. Results included supply voltage variations show that multi-cell upsets dominate soft-error rates. Dual-port SRAM has higher cross-section than single-port SRAM but did not have any multi-cell upset across the bit-line direction. TCAD simulations showing the extent of the perturbation in the electric parameters as a function of particle LET support the experimental data.

引用

页数：5

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