Power-Aware SE Analysis of Different FF Designs at the 14-/16-nm Bulk FinFET CMOS Technology Node

被引：5
|
作者：
Jiang, H. [1 ]
Zhang, H. [1 ]
Chatterjee, I. [2 ]
Kauppila, J. S. [1 ]
Bhuva, B. L. [1 ]
Massengill, L. W. [1 ]
机构：
[1] Vanderbilt Univ, Dept Elect Engn & Comp Sci, 221 Kirkland Hall, Nashville, TN 37235 USA
[2] Airbus Def & Space, D-88090 Immenstaad, Germany
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2018年 / 65卷 / 08期
关键词：
CMOS technology; combinational logic; FinFET; frequency; soft-error rate (SER); FLIP-FLOPS; ERROR RATE; RADIATION; PERFORMANCE; METHODOLOGY; FREQUENCY; CIRCUIT; SYSTEMS; VOLTAGE; RATES;
D O I：
10.1109/TNS.2018.2831002
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As the minimum feature size on an integrated circuit continues to shrink aggressively toward deep submicrometer, the radiation-induced single-event (SE) upset (SEU) has become a prominent concern. Various radiation-hardening-by-design (RHBD) techniques have been developed to achieve a satisfactory SE tolerance for flip-flop (FF) designs. To enable low supply voltage for ICs and overcome the "power wall," the lowest power consumption of different RHBD techniques to meet the target SEU cross section is studied in this paper. A comparative analysis of three representative RHBD FFs and an unhardened FF fabricated at the 14-/16-nm bulk FinFET CMOS technology generation shows that at least 2x power dissipation reduction may be achieved by using RHBD FFs at appropriate supply voltage without degrading SE tolerance.
引用
收藏
页码：1866 / 1871
页数：6
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