Systolic opportunities for multidimensional data streams

被引:9
|
作者
Chai, SM [1 ]
Wills, DS
机构
[1] Motorola Inc, Multimedia Architecture Lab, Schaumburg, IL 60196 USA
[2] Georgia Inst Technol, Microelect Res Ctr, Atlanta, GA 30332 USA
关键词
parallel computer architecture; systolic arrays; area I/O; design and performance evaluation;
D O I
10.1109/71.995819
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Portable image processing applications require an efficient, scalable platform with localized computing regions. This paper presents a new class of area I/O systolic architecture to exploit the physical data locality of planar data streams by processing data where it falls. A synthesis technique using dependence graphs, data partitioning, and computation mapping is developed to handle planar data streams and to systematically design arrays with area I/O. Simulation results show that the use of area I/O provides a 16 times speedup over systems with perimeter I/O. Performance comparisons for a set of signal processing algorithms show that systolic arrays that consider planar data streams in the design process are up to three times faster than traditional arrays.
引用
收藏
页码:388 / 398
页数:11
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