Reducing Timing Side-Channel Information Leakage Using 3D Integration

Recently, following the work pioneered by Kocher [1], using cache behavior as a timing side-channel to leak critical system information has received lots of attentions because of its easy-to-implement nature and amazingly good results. Recent attacks have been demonstrated to successfully leak the full key from many commonly used encryption algorithms including RSA, AES, etc. These attacks pose great threats to applications that depend on these encryption methods such as banking systems, military systems, etc. To mitigate the increasing threat, numerous countermeasures, mostly software patches, have been proposed. Hardware mitigations, however, have been less pursued. 3D integration, which stacks multiple dies vertically, offers shorter wire-length and improves system performance. It may be used to offset the performance overhead these countermeasures incur. In this paper, we investigate several possible ways in which the availability of 3D integration can be exploited to mitigate timing side-channel attacks while still obtaining superior performance over a baseline 2D system. Simulation results using Gem5 simulator show that our techniques can significantly reduce timing information leakage while still achieving 20.43 percent performance gain over a 2D baseline system.