Design Considerations for 60 GHz CMOS Power Amplifiers

被引：0

作者：

He, Ying ^{[1
]}

Zhao, Dixian ^{[1
]}

Li, Lianming ^{[1
]}

Reynaert, Patrick ^{[1
]}

机构：

[1] Katholieke Univ Leuven, ESAT MICAS, Kasteelpk Arenberg 10, B-3001 Leuven, Belgium

来源：

2010 ASIA-PACIFIC MICROWAVE CONFERENCE | 2010年

关键词：

millimeter wave (mm-wave); CMOS; power amplifier; power combining; 60; GHz;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes design considerations for millimeter-wave CMOS power amplifiers (PA). Solutions are presented from device level to circuit level and demonstrated by a measured 60 GHz PA prototype in 65 nm bulk CMOS technology. The proposed PA achieves a peak output power of 14 dBm with a peak power-added efficiency (PAE) of 7.2%. The small signal gain is 10.2 dB and 1-dB compression output power is 10.8 dBm. The transformer-based passives employed in the design enable a compact layout with an active area of 0.3 mm(2). The PA consumes a quiescent current of 143 mA from a 1.6 V supply voltage.

引用

页码：1613 / 1616

页数：4

共 50 条

[31] Design Considerations for Supply Modulated EER Power Amplifiers
Walling, Jeffrey S.
Allstot, David J.
2013 IEEE 14TH ANNUAL WIRELESS AND MICROWAVE TECHNOLOGY CONFERENCE (WAMICON), 2013,
[32] Design Techniques and Considerations for mmWave SiGe Power Amplifiers
Demirel, Nejdat
Kerherve, Eric
Pache, Denis
Plana, Robert
2009 SBMO/IEEE MTT-S INTERNATIONAL MICROWAVE AND OPTOELECTRONICS CONFERENCE (IMOC 2009), 2009, : 37 - +
[33] 60GHz Direct Conversion CMOS Transceiver Design
Matsuzawa, Akira
Okada, Kenichi
2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2011,
[34] Low power considerations and design for CMOS VCOs applied for direct conversion receivers at 5GHz
Adin, Inigo
Quemada, Carlos
Solar, Hector
Sedano, Beatriz
Gutierrez, Inigo
VLSI CIRCUITS AND SYSTEMS III, 2007, 6590
[35] High Data Rate 60 GHz CMOS Transceiver Design
Matsuzawa, Akira
2015 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS), 2015, : 1 - 6
[36] Low-Power 48-GHz CMOS VCO and 60-GHz CMOS LNA for 60-GHz Dual-Conversion Receiver
Lin, Yo-Sheng
Chang, Tien-Hung
Chen, Chang-Zhi
Chen, Chi-Chen
Yang, Hung-Yu
Wong, Simon S.
2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2009, : 88 - +
[37] Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode distributed amplifiers
Liu, RC
Lin, CS
Deng, KL
Wang, H
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (08) : 1370 - 1374
[38] Design of a low power 60GHz OOK receiver in 65nm CMOS technology
Lu, Zhenghao
Feng, Chen
Yu, Xiaopeng
Qin, Yajie
Yeo, Kiat Seng
PROCEEDINGS OF THE 2012 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT), 2012, : 22 - 24
[39] Optimized Design of Low Power 90 nm CMOS Low Noise Amplifier for 60 GHz Applications
Manjula, S.
Suganthy, M.
Anandan, P.
Pown, M.
WIRELESS PERSONAL COMMUNICATIONS, 2024, 136 (03) : 1607 - 1617
[40] Design Techniques for Wideband CMOS Power Amplifiers for Wireless Communications
Lee, Milim
Yang, Junhyuk
Lee, Jaeyong
Park, Changkun
ELECTRONICS, 2024, 13 (09)

← 1 2 3 4 5 →