Concolic Testing of SystemC Designs

被引:0
|
作者
Lin, Bin [1 ]
Cong, Kai [2 ]
Yang, Zhenkun [2 ]
Liao, Zhigang [3 ]
Zhan, Tao [4 ]
Havlicek, Christopher [2 ]
Xie, Fei [1 ]
机构
[1] Portland State Univ, Dept Comp Sci, Portland, OR 97207 USA
[2] Intel Corp, Hillsboro, OR 97124 USA
[3] Virtual Device Technol LLC, Portland, OR 97201 USA
[4] Northwestern Polytech Univ, Sch Comp Sci & Engn, Xian 710072, Shaanxi, Peoples R China
基金
美国国家科学基金会;
关键词
SystemC; concolic testing; code coverage; assertion-based verification; bug detection;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
SystemC is a system-level modelling language widely used in the semiconductor industry. SystemC validation is both necessary and important, since undetected bugs may propagate to final silicon products, which can be extremely expensive and dangerous. However, it is challenging to validate SystemC designs due to their heavy usage of object-oriented features, event-driven simulation semantics, and inherent con-currency. In this paper, we present CTSC, an automated, easy-to-deploy, scalable, and effective binary-level concolic testing framework for SystemC designs. We have implemented CTSC and applied it to an open source SystemC benchmark. In our extensive experiments, the CTSC-generated test cases achieved high code coverage, triggered 14 assertions, and found two severe bugs. In addition, the experiments on two designs with more than 2K lines of SystemC code show that our approach scales to designs of practical sizes.
引用
收藏
页码:1 / 7
页数:7
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