Efficient and effective redundancy removal for million-gate circuits

被引：5
|
作者：
Berkelaar, M
van Eijk, K
机构：
来源：
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/DATE.2002.998445
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：1088 / 1088
页数：1
相关论文
共 50 条
  • [31] Low power modular redundancy: a power efficient fault tolerant approach for digital circuits
    Ansari, Mohammad Saeed
    Mahani, Ali
    Mohammadi, Karim
    COMPEL-THE INTERNATIONAL JOURNAL FOR COMPUTATION AND MATHEMATICS IN ELECTRICAL AND ELECTRONIC ENGINEERING, 2016, 35 (03) : 1098 - 1106
  • [32] Efficient probabilistic method for logic circuits using real delay gate model
    Theodoridis, G.
    Theoharis, S.
    Soudris, D.
    Stouraitis, T.
    Goutis, C.
    Proceedings - IEEE International Symposium on Circuits and Systems, 1999, 1
  • [33] An efficient probabilistic method for logic circuits using real delay gate model
    Theodoridis, G
    Theoharis, S
    Soudris, D
    Stouraitis, T
    Goutis, C
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI, 1999, : 286 - 289
  • [34] REDUNDANCY IDENTIFICATION REMOVAL AND TEST-GENERATION FOR SEQUENTIAL-CIRCUITS USING IMPLICIT STATE ENUMERATION
    CHO, H
    HACHTEL, GD
    SOMENZI, F
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (07) : 935 - 945
  • [35] Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model
    Gagnon, Y
    Savaria, Y
    Meunier, M
    Thibeault, C
    1997 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 1997, : 157 - 165
  • [36] Sweet KNN: An Efficient KNN on GPU through Reconciliation between Redundancy Removal and Regularity
    Chen, Guoyang
    Ding, Yufei
    Shen, Xipeng
    2017 IEEE 33RD INTERNATIONAL CONFERENCE ON DATA ENGINEERING (ICDE 2017), 2017, : 621 - 632
  • [37] Efficient verification of hazard-freedom in gate-level timed asynchronous circuits
    Nelson, CA
    Myers, CJ
    Yoneda, T
    ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2003, : 424 - 431
  • [38] Efficient verification of hazard-freedom in gate-level timed asynchronous circuits
    Nelson, Curtis A.
    Myers, Chris J.
    Yoneda, Tomohiro
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (03) : 592 - 605
  • [39] Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors
    Spagnolo, Fanny
    Corsonello, Pasquale
    Frustaci, Fabio
    Perri, Stefania
    JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS, 2024, 14 (02)
  • [40] Hardware-efficient and fast three-qubit gate in superconducting quantum circuits
    Li, Xiao-Le
    Tao, Ziyu
    Yi, Kangyuan
    Luo, Kai
    Zhang, Libo
    Zhou, Yuxuan
    Liu, Song
    Yan, Tongxing
    Chen, Yuanzhen
    Yu, Dapeng
    FRONTIERS OF PHYSICS, 2024, 19 (05)
12345