Computation Reduction Techniques for Vector Median Filtering and their Hardware Implementation

Vector Median Filters (VMFs) are used in many image and video processing applications. Recently, they are used for Frame Rate Up-Conversion (FRC). However, they are dcult to implement in real-time because of their high computational complexity. Therefore, in this paper, we propose several techniques to reduce the computational complexity of VMFs by using data reuse methodology and by exploiting the spatial correlations in the motion vector field. In addition, we designed and implemented an efficient VMF hardware including the computation reduction techniques exploiting the spatial correlations in the motion vector field on a low cost Xilinx XC3S400A-5 FPGA. The FPGA implementation can work at 145 MHz and it can process more than 94 high definition frames per second.