Copper electroplating to fill blind vias for three-dimensional integration

The continued demand for electronic products with decreased size, higher performance, and increased functionality requires improvements in the system level integration of logic, memory, and other functional integrated circuits. The formation of vertical interconnects in silicon may be one approach to provide this integration. This method involves stacking of individual die to form a highly interconnected three-dimensional structure by placing electrically conductive vias through the body of the silicon to bring the connections from top to bottom. Copper is the metal used to fill the through silicon via structure because of its high conductivity and common use in multilevel wiring. A process will be described in this article to 1 electroplate copper into small diameter (5-10 mu m) vias of aspect ratio > 3. The objective of this project is to develop an electroplating process to obtain a void-free copper filled blind via; a via that does not go through the silicon substrate but terminates inside the silicon. Prior to plating, vias are formed by both reactive ion etch (RIE) and deep RIE processes and are then lined with insulation, barrier, and seed films. The insulation layer, SiO2, is deposited by plasma enhanced chemical vapor deposition while the barrier (TaN) and Cu seed layers are deposited by sputtering. A combination of three electroplating techniques is used in this study to fill the vias. They consist of optimized bath composition (additive control), fountain plating, and reverse pulse plating. The goal during electroplating is to achieve a bottom-up fill, also referred to as "a superfill." This article describes the process that results in void-free electroplating to fill an array of blind vias as well as the related processing issues. (c) 2006 American Vacuum Society.