Formal verification of embedded SoC

被引：1

作者：

Wang, B ^{[1
]}

Lin, ZH ^{[1
]}

机构：

[1] Shanghai Jiao Tong Univ, Inst VLSI, Shanghai 200030, Peoples R China

来源：

2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ICASIC.2001.982676

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

SoC(System on a Chip) are becoming more and more popular due to their widespread applications and the improved techniques. In many cases, the safety is very important. For SoC, the traditional validation techniques, such as simulation and testing, are not viable. Formal methods are becoming a practical alternative to ensure the correctness of the design. In this paper, we investigate the modeling and formal verification of a SoC using Cadence SMV. We use a hierarchical approach to model and formally verify a complete system at different levels.

引用

页码：769 / 772

页数：4

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